Gracefully Degradable Processor Arrays
IEEE Transactions on Computers
A Fault-Tolerant Modular Architecture for Binary Trees
IEEE Transactions on Computers - The MIT Press scientific computation series
IEEE Transactions on Computers
IEEE Transactions on Software Engineering
Supporting fault-tolerant distributed computations under real-time requirements
Computer Communications - Special issue on software aspects of future trends in distributed systems
A Fault-Tolerant Binary Tree Architecture
ICCI '91 Proceedings of the International Conference on Computing and Information: Advances in Computing and Information
Fault-Tolerance in Non-linear Neural Networks
GI - 18. Jahrestagung II, Vernetzte and komplexe Informatik-Systems
Embryonics: A Bio-Inspired Cellular Architecture with Fault-Tolerant Properties
Genetic Programming and Evolvable Machines
Implementing Degradable Processing Arrays
IEEE Micro
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As the demand for highly parallel systems grows, the vast amount of concurrently operating hardware involved can make it difficult to guarantee proper system behavior. Problems arise both from permanent and transient hardware faults and from errors caused by improper programming. A number of fault tolerance solutions have emerged. Following a survey of fault tolerance in arrays, a discussion of solutions for more specialized architectures is presented.