Fault tolerant and fault testable hardware design
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Gracefully Degradable Processor Arrays
IEEE Transactions on Computers
Introduction to real-time software design (2nd ed.)
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Fault-Tolerant Array Processors Using Single-Track Switches
IEEE Transactions on Computers
Adaptation in natural and artificial systems
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Reconfiguration Strategies for VLSI Processor Arrays and Trees Using a Modified Diogenes Approach
IEEE Transactions on Computers
On the OBDD-Representation of General Boolean Functions
IEEE Transactions on Computers
Practical digital logic design and testing
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IEEE Transactions on Computers
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Papers from an international workshop on Towards Evolvable Hardware, The Evolutionary Engineering Approach
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Papers from an international workshop on Towards Evolvable Hardware, The Evolutionary Engineering Approach
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ICES '96 Proceedings of the First International Conference on Evolvable Systems: From Biology to Hardware
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Design of a cell in embryonic systems with improved efficiency and fault-tolerance
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Sliding algorithm for reconfigurable arrays of processors
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IEEE Transactions on Systems, Man, and Cybernetics, Part A: Systems and Humans
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ACM Computing Surveys (CSUR)
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This paper details and expands the work on Embryonics, a recently proposed fault-tolerant cellular architecture with reconfiguration properties inspired by the ontogenetic development of multicellular systems. The design of a selector-based embryonic cell, its applications and the reliability models associated to different embryonic reconfiguration strategies are presented. It is noted that embryonic distributed systems possess, in the majority of cases, better reliability characteristics than equivalent centralised systems.