Fault tolerant and fault testable hardware design
Fault tolerant and fault testable hardware design
A Fault-Tolerant Modular Architecture for Binary Trees
IEEE Transactions on Computers - The MIT Press scientific computation series
Fault-Tolerant Array Processors Using Single-Track Switches
IEEE Transactions on Computers
Embryonics: A Bio-Inspired Cellular Architecture with Fault-Tolerant Properties
Genetic Programming and Evolvable Machines
Reliability analysis of tree, torus and hypercube message passing architectures
SSST '97 Proceedings of the 29th Southeastern Symposium on System Theory (SSST '97)
An improved reconfiguration algorithm for degradable VLSI/WSI arrays
Journal of Systems Architecture: the EUROMICRO Journal
Fault Tolerance in Binary Tree Architectures
IEEE Transactions on Computers
SFCS '80 Proceedings of the 21st Annual Symposium on Foundations of Computer Science
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Electronic systems with intrinsic adaptive and evolvable features can potentially significantly increase functionality of a system. To achieve high level of adaptivity the system must be able to modify its internal configuration under changing environmental conditions without interrupting operation. This can be achieved through dynamic reconfiguration. Dynamic reconfiguration of arrays of processors often relies on the specialized architectures with the built-in reconfiguration capacities. Specialized architectures suffer from lack of flexibility and high cost. Reconfiguration algorithms for highly practical general purpose architectures such as rectangular grid of processors are highly complex and, thus, unsuitable for dynamic reconfiguration. This paper proposes a systematic approach to reconfigurable architectures. The general framework for reconfiguration algorithms design is presented based on discrete Morse functions and discrete vector fields on cellular complexes.