Communications of the ACM
X-Tree: A tree structured multi-processor computer architecture
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
A Graph Model for Fault-Tolerant Computing Systems
IEEE Transactions on Computers
A Fault-Tolerant Modular Architecture for Binary Trees
IEEE Transactions on Computers - The MIT Press scientific computation series
Distributed Recovery in Fault-Tolerant Multiprocessor Networks
IEEE Transactions on Computers
Reconfigurable Tree Architectures Using Subtree Oriented Fault Tolerance
IEEE Transactions on Computers
Distributed fault-tolerance of tree structures
IEEE Transactions on Computers
Gracefully Degradable Pipeline Networks
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
Sliding algorithm for reconfigurable arrays of processors
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
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Binary tree network architectures are applicable in the design of hierarchical computing systems and in specialized high-performance computers. In this correspondence, the reliability and fault tolerance issues in binary tree architecture with spares are considered. Two different fault-tolerance mechanisms are described and studied, namely: 1) scheme with spares; and 2) scheme with performance degradation. Reliability analysis and estimation of the fault-tolerant binary tree structures are performed using the interactive ARIES 82 program. The discussion is restricted to the topological level, and certain extensions of the schemes are also discussed.