Distributed fault-tolerance for large multiprocessor systems
ISCA '80 Proceedings of the 7th annual symposium on Computer Architecture
X-Tree: A tree structured multi-processor computer architecture
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Design and simulation of the distributed loop computer network (DLCN)
ISCA '76 Proceedings of the 3rd annual symposium on Computer architecture
A large scale, homogeneous, fully distributed parallel machine, I
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Fault Tolerance in Binary Tree Architectures
IEEE Transactions on Computers
A Graph Model for Fault-Tolerant Computing Systems
IEEE Transactions on Computers
Hypertree: A Multiprocessor Interconnection Topology
IEEE Transactions on Computers
Bi-Level Reconfigurations of Fault Tolerant Arrays
IEEE Transactions on Computers
Efficient Distributed Algorithms for Self Testing of Multiple Processor Systems
IEEE Transactions on Computers
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Tree structures, as the interconnection structure in networks of many processing elements, have interesting features such as regularity ease of expansion, simple routing, simple addressing, suitability for VLSI/WSI implementation, etc. Distributed fault tolerance of these networks is considered. It is assumed that in these structures, there does not exist any central failure-free entity for providing services such as diagnosis of faulty components, system reconfiguration after failure, control, or coordination among the processing elements. Every processing element is able to diagnose the condition of every other node or internode communication paths via a truly distributed scheme.