Configuration of VLSI Arrays in the Presence of Defects
Journal of the ACM (JACM)
Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems
IEEE Transactions on Computers
IEEE Transactions on Computers
Algorithm 457: finding all cliques of an undirected graph
Communications of the ACM
A reconfigurable and fault-tolerant VLSI multiprocessor array
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Real time fault tolerant computing for vlsi processor arrays
Real time fault tolerant computing for vlsi processor arrays
Mapping/matching algorithms to reconfigurable mesh arrays
Mapping/matching algorithms to reconfigurable mesh arrays
Graph theory: An algorithmic approach (Computer science and applied mathematics)
Graph theory: An algorithmic approach (Computer science and applied mathematics)
Efficient Algorithms for Reconfiguration in VLSI/WSI Arrays
IEEE Transactions on Computers
A fast algorithm for connecting grid points to the boundary with nonintersecting straight lines
SODA '91 Proceedings of the second annual ACM-SIAM symposium on Discrete algorithms
IEEE Transactions on Computers
A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors
IEEE Transactions on Computers
Reconfiguration Models and Algorithms for Stateful Interactive Processes
IEEE Transactions on Software Engineering
On finding non-intersecting paths in grids and its application in reconfiguring VLSI/WSI arrays
SODA '90 Proceedings of the first annual ACM-SIAM symposium on Discrete algorithms
Fault-Tolerant Processor Arrays Using Additional Bypass Linking Allocated by Graph-Node Coloring
IEEE Transactions on Computers
IEEE Transactions on Computers
An Efficient Reconfiguration Algorithm for Degradable VLSI/WSI Arrays
IEEE Transactions on Computers
Embryonics: A Bio-Inspired Cellular Architecture with Fault-Tolerant Properties
Genetic Programming and Evolvable Machines
Implementing Degradable Processing Arrays
IEEE Micro
A Polynomial Time Algorithm for Reconfiguring Multiple-Track Models
IEEE Transactions on Computers
Reconfigurability and Reliability of Systolic/Wavefront Arrays
IEEE Transactions on Computers
Fault-Tolerant Meshes and Hypercubes with Minimal Numbers of Spares
IEEE Transactions on Computers
Yield Analysis of Reconfigurable Array Processors Based on Multiple-Level Redundancy
IEEE Transactions on Computers
Reconfiguring Processor Arrays Using Multiple-Track Models: The 3Track-Spare-Approach
IEEE Transactions on Computers
Computational Arrays with Flexible Redundancy
IEEE Transactions on Computers
Routing in Modular Fault-Tolerant Multiprocessor Systems
IEEE Transactions on Parallel and Distributed Systems
Totally defect-tolerant arrays capable of quick broadcasting
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
A Channel-Constrained Reconfiguration Approach for Processing Arrays
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Reconfigurable architectures for mesh-arrays with PE and link faults
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Spare processor allocation for fault tolerance in torus-based multicomputers
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sliding algorithm for reconfigurable arrays of processors
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
A dynamically reconfigurable interconnect for array processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An FPGA-based fault-tolerant 2D systolic array for matrix multiplications
Transactions on computational science XIII
Proceedings of the Conference on Design, Automation and Test in Europe
A Region-based Fault-Tolerant Routing Algorithmfor 2D Irregular Mesh Network-on-Chip
Journal of Electronic Testing: Theory and Applications
| Hi-index | 15.02 |
An array grid model based on single-track switches is proposed. A reconfigurability theorem is developed to provide the theoretical footing for novel reconfiguration algorithms for the fabrication-time and run-time processing. For fabrication-time yield enhancement, the problem of finding a feasible reconfiguration using global control can be reformulated as a maximum independent set problem. An existing algorithm in graph theory is adopted to solve this problem. The simulations conducted indicate that the algorithm is computationally very efficient; therefore, it may also be applicable to certain run-time fault tolerance. In real-time fault tolerance, the propagation time of data/control signals between the host computer incurred in the global control is often prohibitively long; therefore, only distributed processing is feasible. Based on the same reconfigurability theorem, a distributive reconfiguration algorithm is developed for (asynchronous) array processors.