Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array

  • Authors:
  • Zoltán Endre Rákossy;Masayuki Hiromoto;Hiroshi Tsutsui;Takashi Sato;Yukihiro Nakamura;Hiroyuki Ochi

  • Affiliations:
  • Kyoto University, Yoshida-honmachi, Sakyo, Kyoto, Japan;Kyoto University, Yoshida-honmachi, Sakyo, Kyoto, Japan;Kyoto University, Yoshida-honmachi, Sakyo, Kyoto, Japan;Kyoto University, Yoshida-honmachi, Sakyo, Kyoto, Japan;Ritsumeikan University, Noji-higashi, Kusatsu, Shiga, Japan;Kyoto University, Yoshida-honmachi, Sakyo, Kyoto, Japan

  • Venue:
  • Proceedings of the Conference on Design, Automation and Test in Europe
  • Year:
  • 2013

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Abstract

Due to latest advances in semiconductor integration, systems are becoming more susceptible to faults leading to temporary or permanent failures. We propose a new architecture extension suitable for arrays of functional units (FUs), that will provide testing and replacement of faulty units, without interrupting normal system operation. The extension relies on datapath switching realized by the proposed hot-swapping algorithm and structures, by use of which functional units are tested and replaced by spares, at lower overheads than traditional modular redundancy. For a case study architecture, hot-swapping support could be added with only 29% area overhead. In this paper we focus on experimental evaluation of the hot-swapping system from a fabricated chip in 65nm CMOS process. Autonomous testing of the hot-swapping system is enhanced with back-bias circuitry to attain an early fault detection and restoration system. Experimental measurements prove that the proposed concept works well, predicting fault occurrence with a configurable prediction interval, while power measurements reveal that with only 20 % power overhead the proposed system can attain reliability levels similar to triple modular redundancy. Additionally, measurements reveal that manufacturing randomness across the die can significantly influence identical sub-circuit reliability located in different parts in the die, although identical layout has been employed.