Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
A Fortran language system for mutation-based software testing
Software—Practice & Experience
Reliable computer systems (2nd ed.): design and evaluation
Reliable computer systems (2nd ed.): design and evaluation
On error correction in macro-based circuits
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Logic clause analysis for delay optimization
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Design verification via simulation and automatic test pattern generation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Multiple error diagnosis based on xlists
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A logic verifier based on Boolean comparison
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Formal Verification of Hardware Design
Formal Verification of Hardware Design
Quantifying Design Quality Through Design Experiments
IEEE Design & Test
Commercial Design Verification: Methodology and Tools
Proceedings of the IEEE International Test Conference on Test and Design Validity
Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis
Proceedings of the IEEE International Test Conference
High-coverage ATPG for datapath circuits with unimplemented blocks
ITC '98 Proceedings of the 1998 IEEE International Test Conference
ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Lifetime validation of digital systems via fault modeling and test generation
Lifetime validation of digital systems via fault modeling and test generation
A novel framework for logic verification in a synthesis environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Perturb and simplify: multilevel Boolean network optimizer
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Logic optimization and equivalence checking by implication analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exclusive Test and its Applications to Fault Diagnosis
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Incremental Design Debugging in a Logic Synthesis Environment
Journal of Electronic Testing: Theory and Applications
Deployment of Better Than Worst-Case Design: Solutions and Needs
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Proceedings of the Conference on Design, Automation and Test in Europe
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We investigate an automated design validation scheme for gate-level combinational and sequential circuits that borrows methods from simulation and test generation for physical faults, and verifies a circuit with respect to a modeled set of design errors. The error models used in prior research are examined and reduced to five types: gate substitution errors (GSEs), gate count errors (GCEs), input count errors (ICEs), wrong input errors (WIEs), and latch count errors (LCEs). Conditions are derived for a gate to be testable for GSEs, which lead to small, complete test sets for GSEs; near-minimal test sets are also derived for GCEs. We analyze undetectability in design errors and relate it to single stuck-line (SSL) redundancy. We show how to map all the foregoing error types into SSL faults, and describe an extensive set of experiments to evaluate the proposed method. These experiments demonstrate that high coverage of the modeled errors can be achieved with small test sets obtained with standard test generation and simulation tools for physical faults.