A novel framework for logic verification in a synthesis environment

Authors:
W. Kunz;D. K. Pradhan;S. M. Reddy
Affiliations:
Group for Fault-Tolerant Comput., Univ. of Potsdam;-;-
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2006

Citing 0
Cited 10

VERILAT: verification using logic augmentation and transformations

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Tight integration of combinational verification methods

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
An Efficient Logic Equivalence Checker for Industrial Circuits

Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Logic Design Validation via Simulation and Automatic Test Pattern Generation

Journal of Electronic Testing: Theory and Applications
Solving the latch mapping problem in an industrial setting

Proceedings of the 40th annual Design Automation Conference
Learning from BDDs in SAT-based bounded model checking

Proceedings of the 40th annual Design Automation Conference
Logic verification based on diagnosis techniques

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Mining global constraints for improving bounded sequential equivalence checking

Proceedings of the 43rd annual Design Automation Conference
Fast co-verification of HDL models

Microelectronic Engineering

Quantified Score

Hi-index	0.03

Visualization

Abstract

A new methodology for formal logic verification of combinational circuits is presented. Specifically, a structural (logic network) approach is used, based on indirect implications derived by recursive learning. It is shown that implications can be used to capture similarity between designs. This is extended to formulate a hybrid approach, this structural (logic network) information is used to reduce the complexity of a subsequent functional method based on OBDDs. We demonstrate that OBDD-based verification can take great advantage of structural preprocessing in a synthesis environment where many small operations are performed that modify the circuit. The experimental results show that an effective combination can be achieved between memory efficient structural methods and powerful functional methods