Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
EST: The new frontier in automatic test-pattern generation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Logic verification methodology for PowerPC microprocessors
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Advanced verification techniques based on learning
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An efficient equivalence checker for combinational circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
HANNIBAL: an efficient tool for logic verification based on recursive learning
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
Commercial Design Verification: Methodology and Tools
Proceedings of the IEEE International Test Conference on Test and Design Validity
Switch-Level ATPG Using Constraint-Guided Line Justification
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A novel framework for logic verification in a synthesis environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present our formal combinational logic equivalencechecking methods forindustry-sized circuits. Our methods employ functional (OBDDs) algorithms fordecisions on logic equivalence and structural (ATPG) algorithms to quicklyidentify inequivalence. The complimentary strengths of the two types ofalgorithms result in a significant reduction in CPU time. Our methods alsoinvolve analytical and empirical heuristics whose impact on performance forindustrial designs is considerable. The combination of OBDDs, ATPG, and ourheuristics resulted in a decrease in CPU time of up to 80% over OBDDs alonefor the circuits we tested. In addition, we describe an algorithm forautomatically determining the correspondence between storage elements in thedesigns being compared.