An efficient equivalence checker for combinational circuits

VERILAT: verification using logic augmentation and transformations

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Equivalence checking using cuts and heaps

DAC '97 Proceedings of the 34th annual Design Automation Conference

An efficient assertion checker for combinational properties

DAC '97 Proceedings of the 34th annual Design Automation Conference

Tight integration of combinational verification methods

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

An efficient filter-based approach for combinational verification

DATE '99 Proceedings of the conference on Design, automation and test in Europe

Combinational equivalence checking using satisfiability and recursive learning

DATE '99 Proceedings of the conference on Design, automation and test in Europe

AQUILA: An Equivalence Checking System for Large Sequential Designs

IEEE Transactions on Computers

An Efficient Logic Equivalence Checker for Industrial Circuits

Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification

Using SAT for combinational equivalence checking

Proceedings of the conference on Design, automation and test in Europe

Combinational equivalence checking using Boolean satisfiability and binary decision diagrams

Proceedings of the conference on Design, automation and test in Europe

Automatic partitioning for efficient combinatorial verification

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference

Combinational and sequential equivalence checking

Logic Synthesis and Verification

Verification of integer multipliers on the arithmetic bit level

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design

Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table

Formal Methods in System Design

Applied Boolean Equivalence Verification and RTL Static Sign-Off

IEEE Design & Test

Simplifying Circuits for Formal Verification Using Parametric Representation

FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design

CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination

CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification

SAT and ATPG: Boolean engines for formal hardware verification

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Formal Verification of Combinational Circuit

VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

Efficient equivalence checking with partitions and hierarchical cut-points

Proceedings of the 41st annual Design Automation Conference

An effective and efficient ATPG-based combinational equivalence checker

GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI

Refactoring digital hardware designs with assertion libraries

HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop

Logic verification based on diagnosis techniques

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

Improvements to combinational equivalence checking

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems

IEEE Transactions on Computers

Verification Techniques for System-Level Design

Verification Techniques for System-Level Design

A BDD-based verification method for large synthesized circuits

Integration, the VLSI Journal