Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Advanced verification techniques based on learning
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An efficient equivalence checker for combinational circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
VERILAT: verification using logic augmentation and transformations
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
A novel framework for logic verification in a synthesis environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using SAT for combinational equivalence checking
Proceedings of the conference on Design, automation and test in Europe
Combinational equivalence checking using Boolean satisfiability and binary decision diagrams
Proceedings of the conference on Design, automation and test in Europe
An efficient learning procedure for multiple implication checks
Proceedings of the conference on Design, automation and test in Europe
An efficient solution to the storage correspondence problem for large sequential circuits
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Circuit-based Boolean Reasoning
Proceedings of the 38th annual Design Automation Conference
Dynamic detection and removal of inactive clauses in SAT with application in image computation
Proceedings of the 38th annual Design Automation Conference
A proof engine approach to solving combinational design automation problems
Proceedings of the 39th annual Design Automation Conference
Combinational and sequential equivalence checking
Logic Synthesis and Verification
SIVA: A System for Coverage-Directed State Space Search
Journal of Electronic Testing: Theory and Applications
Partition-based decision heuristics for image computation using SAT and BDDs
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Applied Boolean Equivalence Verification and RTL Static Sign-Off
IEEE Design & Test
SAT-Based Image Computation with Application in Reachability Analysis
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Solving the latch mapping problem in an industrial setting
Proceedings of the 40th annual Design Automation Conference
Checking satisfiability of a conjunction of BDDs
Proceedings of the 40th annual Design Automation Conference
Learning from BDDs in SAT-based bounded model checking
Proceedings of the 40th annual Design Automation Conference
Identifying Redundant Gate Replacements in Verification by Error Modeling
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Design Verification by Test Vectors and Arithmetic Transform Universal Test Set
IEEE Transactions on Computers
Efficient equivalence checking with partitions and hierarchical cut-points
Proceedings of the 41st annual Design Automation Conference
Verification of Proofs of Unsatisfiability for CNF Formulas
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
On equivalence checking and logic synthesis of circuits with a common specification
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
An effective and efficient ATPG-based combinational equivalence checker
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Integrating CNF and BDD based SAT solvers
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
BerkMin: A fast and robust Sat-solver
Discrete Applied Mathematics
CirCUs: a hybrid satisfiability solver
SAT'04 Proceedings of the 7th international conference on Theory and Applications of Satisfiability Testing
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