An efficient solution to the storage correspondence problem for large sequential circuits

Authors:
Wanlin Cao;Duncan M. H. Walker;Rajarshi Mukherjee
Affiliations:
Department of Computer Science Texas A&M University, College Station, TX;Department of Computer Science Texas A&M University, College Station, TX;Fujitsu Laboratories of America, 595 Lawrence Expressway, Sunnyvale, CA
Venue:
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Year:
2001

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Abstract

Traditional state-traversal-based methods for verifying sequential circuits are computationally infeasible for circuits with a large number of memory elements. However, if the correspondence of the memory elements of the two circuits can be established, a difficult sequential verification problem can be transformed into an easier combinational verification problem. In this paper, we propose an approach that combines two complementary simulation-based methods for fast and accurate storage correspondence. Experiments on the large ISCAS89 benchmark circuits demonstrate the superiority.