VERILAT: verification using logic augmentation and transformations
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
Sequential equivalence checking without state space traversal
Proceedings of the conference on Design, automation and test in Europe
An efficient solution to the storage correspondence problem for large sequential circuits
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A practical and efficient method for compare-point matching
Proceedings of the 39th annual Design Automation Conference
Combinational and sequential equivalence checking
Logic Synthesis and Verification
Solving the latch mapping problem in an industrial setting
Proceedings of the 40th annual Design Automation Conference
Efficient equivalence checking with partitions and hierarchical cut-points
Proceedings of the 41st annual Design Automation Conference
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Visibility enhancement for silicon debug
Proceedings of the 43rd annual Design Automation Conference
Boosting the role of inductive invariants in model checking
Proceedings of the conference on Design, automation and test in Europe
Verification Techniques for System-Level Design
Verification Techniques for System-Level Design
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