Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
Record & play: a structural fixed point iteration for sequential circuit verification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Robust latch mapping for combinational equivalence checking
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Tight integration of combinational verification methods
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
AQUILA: An Equivalence Checking System for Large Sequential Designs
IEEE Transactions on Computers
A practical and efficient method for compare-point matching
Proceedings of the 39th annual Design Automation Conference
A novel framework for logic verification in a synthesis environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient filter-based approach for combinational verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sequential equivalence checking based on structural similarities
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploiting suspected redundancy without proving it
Proceedings of the 42nd annual Design Automation Conference
Verification Techniques for System-Level Design
Verification Techniques for System-Level Design
Optimal redundancy removal without fixedpoint computation
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
| Hi-index | 0.00 |
We describe a complete method for the latch mapping problem that is based on the efficient integration of previously proposed techniques for latch mapping as well as novel optimizations for further improvement. The highlights of the proposed approach include a new method of integrating complete methods and incomplete methods for latch mapping, the use of incremental reasoning to optimize the overall algorithm and the use of a conventional combinational equivalence checking tool as the core engine. Experiments confirm that the proposed method retains much of the efficiency and capacity of incomplete methods while providing the completeness of complete methods and derives significant performance improvements from the proposed optimizations.