Combinational and sequential equivalence checking
Logic Synthesis and Verification
Solving the latch mapping problem in an industrial setting
Proceedings of the 40th annual Design Automation Conference
Principles of Sequential-Equivalence Verification
IEEE Design & Test
Sequential equivalence checking using cuts
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Improvements to combinational equivalence checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Boosting the role of inductive invariants in model checking
Proceedings of the conference on Design, automation and test in Europe
Inductive equivalence checking under retiming and resynthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Compositional verification of retiming and sequential optimizations
Proceedings of the 45th annual Design Automation Conference
Merging nodes under sequential observability
Proceedings of the 45th annual Design Automation Conference
Functional Verification of Power Gated Designs by Compositional Reasoning
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Scalable and scalably-verifiable sequential synthesis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Invariant-strengthened elimination of dependent state elements
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Recording synthesis history for sequential verification
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Functional verification of power gated designs by compositional reasoning
Formal Methods in System Design
Non-cycle-accurate sequential equivalence checking
Proceedings of the 46th Annual Design Automation Conference
Strengthening model checking techniques with inductive invariants
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sequential logic synthesis using symbolic bi-decomposition
Proceedings of the Conference on Design, Automation and Test in Europe
Speeding up model checking by exploiting explicit and hidden verification constraints
Proceedings of the Conference on Design, Automation and Test in Europe
Sechecker: a sequential equivalence checking framework based on K th invariants
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the danger of coverage directed test case generation
FASE'12 Proceedings of the 15th international conference on Fundamental Approaches to Software Engineering
Proceedings of the 34th International Conference on Software Engineering
Observable modified Condition/Decision coverage
Proceedings of the 2013 International Conference on Software Engineering
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Checking the functional equivalence of sequential circuits is an important practical problem. Because general algorithms for solving this problem require a state-space traversal of the product machine, they are computationally expensive. In this paper, we present a new method for sequential equivalence checking which utilizes functionally equivalent signals to prove the equivalence of both circuits, thereby avoiding the state-space traversal. The effectiveness of the proposed method is confirmed by experimental results on retimed and optimized ISCAS'89 benchmarks