Sequential equivalence checking using cuts

Authors:
Wei Huang;PuShan Tang;Min Ding
Affiliations:
Fudan University, Shanghai, China;Fudan University, Shanghai, China;Fudan University, Shanghai, China
Venue:
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Year:
2005

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Abstract

This paper presents an algorithm which is an improvement of Van Eijk's Algorithm[5] by incorporating a cutpoints technique[8]. Combinational verification often uses the technique to convert large scale circuits to several small ones, which will be verified separately. Reasonable cuts can bring less time consuming to combinational verification. We embed the technique into sequential equivalence checking. Experimental results show that the proposed method can achieve about 2x speedup over the original one.