Algorithms for solving Boolean satisfiability in combinational circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Boolean satisfiability in electronic design automation
Proceedings of the 37th Annual Design Automation Conference
An efficient learning procedure for multiple implication checks
Proceedings of the conference on Design, automation and test in Europe
An exact solution to the minimum size test pattern problem
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SAT with partial clauses and back-leaps
Proceedings of the 39th annual Design Automation Conference
New Techniques for Deterministic Test Pattern Generation
Journal of Electronic Testing: Theory and Applications
Pruning Techniques for the SAT-Based Bounded Model Checking Problem
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Conflict driven techniques for improving deterministic test pattern generation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
20.2 New Techniques for Deterministic Test Pattern Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
STAR-ATPG: A High Speed Test Pattern Generator for Large Scan Designs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Accelerating Bounded Model Checking of Safety Properties
Formal Methods in System Design
PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Sequential equivalence checking using cuts
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
SymChaff: a structure-aware satisfiability solver
AAAI'05 Proceedings of the 20th national conference on Artificial intelligence - Volume 1
SAT-Solving in Practice, with a Tutorial Example from Supervisory Control
Discrete Event Dynamic Systems
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics
Journal of Electronic Testing: Theory and Applications
Incremental solving techniques for SAT-based ATPG
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A SAT-based Method for Solving the Two-dimensional Strip Packing Problem
Fundamenta Informaticae - RCRA 2008 Experimental Evaluation of Algorithms for Solving Problems with Combinatorial Explosion
Applying SMT in symbolic execution of microcode
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Boosting minimal unsatisfiable core extraction
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Simultaneous SAT-Based model checking of safety properties
HVC'05 Proceedings of the First Haifa international conference on Hardware and Software Verification and Testing
iSat: structure visualization for SAT problems
LPAR'12 Proceedings of the 18th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
Efficient SAT solving under assumptions
SAT'12 Proceedings of the 15th international conference on Theory and Applications of Satisfiability Testing
Implicative simultaneous satisfiability and applications
HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing
Techniques for SAT-based constrained test pattern generation
Microprocessors & Microsystems
LFSR seed computation and reduction using SMT-based fault-chaining
Proceedings of the Conference on Design, Automation and Test in Europe
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In recent years several highly effective algorithms have been proposed for Automatic Test Pattern Generation (ATPG). Nevertheless, most of these algorithms too often rely on different types of heuristics to achieve good empirical performance. Moreover, there has not been significant research work on developing algorithms that are robust, in the sense that they can handle most faults with little heuristic guidance. In this paper we describe an algorithm for ATPG that is robust and still very efficient. In contrast with existing algorithms for ATPG, the proposed algorithm reduces heuristic knowledge to a minimum and relies on an optimized search algorithm for effectively pruning the search space. Even though the experimental results are obtained using an ATPG tool built on top of a Propositional Satisfiability (SAT) algorithm, the same concepts can be integrated on application-specific algorithms.