Solving the incremental satisfiability problem
Journal of Logic Programming
BiTeS: a BDD based test pattern generator for strong robust path delay faults
EURO-DAC '94 Proceedings of the conference on European design automation
A satisfiability-based test generator for path delay faults in combinational circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
On applying incremental satisfiability to delay fault testing
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Robust Search Algorithms for Test Pattern Generation
FTCS '97 Proceedings of the 27th International Symposium on Fault-Tolerant Computing (FTCS '97)
TranGen: a SAT-based ATPG for path-oriented transition faults
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A Circuit SAT Solver With Signal Correlation Guided Learning
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Selection of Paths for Delay Testing
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
Reusing Learned Information in SAT-based ATPG
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
BerkMin: A fast and robust Sat-solver
Discrete Applied Mathematics
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults
MEMOCODE '07 Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign
On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation
Journal of Electronic Testing: Theory and Applications
On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults
ISMVL '08 Proceedings of the 38th International Symposium on Multiple Valued Logic
TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques
ETS '09 Proceedings of the 2009 European Test Symposium
Test Pattern Generation using Boolean Proof Engines
Test Pattern Generation using Boolean Proof Engines
NEST: a nonenumerative test generation method for path delay faults in combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast nonenumerative automatic test pattern generator for path delay faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Critical path selection for delay fault testing based upon a statistical timing model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On Acceleration of SAT-Based ATPG for Industrial Designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SAT-based generation of compressed skewed-load tests for transition delay faults
Microprocessors & Microsystems
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As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to detect small delay defects and to verify the correct temporal behavior of a circuit. In this article, MONSOON, an efficient SAT-based approach for generating non-robust and robust test patterns for path delay faults is presented. MONSOON handles tri-state elements and environmental constraints occurring in industrial practice using multiple-valued logics. Structural techniques increase the efficiency of the algorithm. A comparison with a state-of-the-art approach shows a significant speed-up. Experimental results for large industrial circuits demonstrates the feasibility and robustness of MONSOON.