Efficiency of Multi-Valued Encoding in SAT-based ATPG
ISMVL '06 Proceedings of the 36th International Symposium on Multiple-Valued Logic
Experimental Studies on SAT-Based ATPG for Gate Delay Faults
ISMVL '07 Proceedings of the 37th International Symposium on Multiple-Valued Logic
Layout-aware scan chain reorder for launch-off-shift transition test coverage
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test Pattern Generation using Boolean Proof Engines
Test Pattern Generation using Boolean Proof Engines
A novel test application scheme for high transition fault coverage and low test cost
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics
Journal of Electronic Testing: Theory and Applications
Chiba Scan Delay Fault Testing with Short Test Application Time
Journal of Electronic Testing: Theory and Applications
Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG
DSD '10 Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
Techniques for SAT-Based Constrained Test Pattern Generation
DSD '11 Proceedings of the 2011 14th Euromicro Conference on Digital System Design
On the Computation of Common Test Data for Broadside and Skewed-Load Tests
IEEE Transactions on Computers
Combinational test generation using satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Delay-fault test generation and synthesis for testability under a standard scan design methodology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reducing correlation to improve coverage of delay faults in scan-path design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Skewed-load tests ensure application of delay tests to logic cores of system-on-chip with only one storage element per cell in the wrapper boundary register and in the internal scan chain. This resolves the test area problem but the fault coverage and the test application time still require optimization efforts. The satisfiability-based test pattern generator of compressed skewed-load tests for transition delay fault is proposed. It represents a new efficient approach for generating compressed skewed-load tests because the test is gradually generated without the need of a pre-generated set of initialization and excitation vectors. Two optimization methods are also proposed. The first method, the wrapper cell ordering method, increases the fault coverage by reducing the shift dependence of skewed-load tests. The second method, the fault ordering method, ensures shorter tests by determining the order in which the faults will be targeted during the test generation and consequently, the new test vectors can overlap the test sequence in the greatest degree. The proposed methods were evaluated over benchmark circuits and the experimental results show higher fault coverages and shorter test lengths.