Achieving low capture and shift power in linear decompressor-based test compression environment
Microelectronics Journal
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SAT-based generation of compressed skewed-load tests for transition delay faults
Microprocessors & Microsystems
Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection
Proceedings of the Conference on Design, Automation and Test in Europe
Generation of mixed test sets for transition faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Built-in generation of functional broadside tests using a fixed hardware structure
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Broadside and skewed-load tests under primary input constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test compaction for small-delay defects using an effective path selection scheme
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Built-in generation of multicycle functional broadside tests with observation points
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design-for-testability for multi-cycle broadside tests by holding of state variables
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-power test sets under test-related primary input constraints
International Journal of Critical Computer-Based Systems
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A broad-side delay test is a form of a scan-based delay test, where the first vector of the pair is scanned into the chain and the second vector of the pair is the combinational circuit's response to this first vector. This delay test form is called “broad-side” since the second vector of the delay test pair is provided in a broad-side fashion, namely through the logic. This paper concentrates on several issues concerning broad-side delay test. It analyzes the effectiveness of broad-side delay test; shows how to compute broad-side delay test vectors; shows how to generate broad-side delay test vectors using existing tools that were aimed at stuck-at faults; shows how to compute the detection probability of a transition fault using broad-side pseudo-random patterns; shows the results of experiments conducted on the ISCAS sequential benchmarks; and discusses some concerns of the broad-side delay test strategy. It is shown that the broad-side method is inferior to the skewed-load method, which is another form of scan-based transition test. There is, however, a merit in combining the skewed-load method with the broad-side method. This combined method will achieve a higher transition fault coverage than each individual method alone