At-speed delay testing of synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A variable observation time method for testing delay faults
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Design-for-testability for path delay faults in large combinatorial circuits using test-points
DAC '94 Proceedings of the 31st annual Design Automation Conference
DFT Strategy for Intel Microprocessors
Proceedings of the IEEE International Test Conference on Test and Design Validity
IDDQ and AC Scan: The War Against Unmodelled Defects
Proceedings of the IEEE International Test Conference on Test and Design Validity
Pentium® Pro Processor Design for Test and Debug
Proceedings of the IEEE International Test Conference
Too much delay fault coverage is a bad thing
Proceedings of the IEEE International Test Conference 2001
Debug methodology for the McKinley processor
Proceedings of the IEEE International Test Conference 2001
Test generation for designs with multiple clocks
Proceedings of the 40th annual Design Automation Conference
Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Logic BIST Using Constrained Scan Cells
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Improving the transition fault coverage of functional broadside tests by observation point insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Generation of Functional Broadside Tests for Transition Faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimized test application timing for AC test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Transition fault testing for sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test application time reduction for sequential circuits with scan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Generation of Multi-Cycle Broadside Tests
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Built-in generation of functional broadside tests using a fixed hardware structure
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Functional broadside tests allow overtesting to be avoided as part of a scheme that considers both test generation and the analysis of output responses, by ensuring that delay faults are detected under functional operation conditions. Compared with two-cycle tests, multicycle tests allow more faults to be detected with each test, thus reducing the number of tests that need to be applied. They also provide an opportunity for nonfunctional electrical effects, which are caused by switching between modes of operation, to subside before the clock cycles where delay faults are detected. Built-in test generation facilitates at-speed testing and reduces the test data volume. Motivated by these observations, this article describes the modification of a built-in test generation method for two-cycle functional broadside tests so as to generate multicycle functional broadside tests. The size of the hardware is not increased by the modification. The article investigates the following issues related to this method: (1) the effect of using multicycle tests on the number of tests that need to be applied; (2) fault simulation for tailoring the test generation hardware to a circuit that takes into account, to different extents, the need to allow nonfunctional electrical effects to subside; (3) the insertion of observation points in order to increase the transition fault coverage.