A simplified six-waveform type method for delay fault testing
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Correlation-reduced scan-path design to improve delay fault coverage
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A quantitative measure of robustness for delay fault testing
EURO-DAC '92 Proceedings of the conference on European design automation
Design-for-testability for path delay faults in large combinatorial circuits using test-points
DAC '94 Proceedings of the 31st annual Design Automation Conference
Delay Fault Coverage Enhancement Using Variable Observation Times
Journal of Electronic Testing: Theory and Applications
Timing simulation of digital circuits with binary decision diagrams
Proceedings of the conference on Design, automation and test in Europe
Enhancing test efficiency for delay fault testing using multiple-clocked schemes
Proceedings of the 39th annual Design Automation Conference
Generation of tenacious tests for small gate delay faults in combinational circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
Gate delay fault test generation for non-scan circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
DFSIM: A Gate-Delay Fault Simulator for Sequential Circuits
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Delay Fault Coverage Enhancement Using Multiple Test Observation Times
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
What Does Robust Testing a Subset of Paths, Tell us about the Untested Paths in the Circuit?
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip
Journal of Electronic Testing: Theory and Applications
Diagnosis framework for locating failed segments of path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improving the transition fault coverage of functional broadside tests by observation point insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
On-Chip Delay Measurement Based Response Analysis for Timing Characterization
Journal of Electronic Testing: Theory and Applications
Built-in generation of multicycle functional broadside tests with observation points
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Test methodologies for delay faults usually observe output patterns at a single observation time, and the same observation time is used for all faults in the circuit under test. In this paper we show that use of a single observation time is not advantageous for testing delay faults, and we are able to show that the detection threshold can be dramatically improved by using a testing methodology that allows variable, fault-dependent and output-dependent observation times. A “waveform-type” simulation method is used for calculating detection thresholds for definitely detectable faults. Statistical distributions of delay fault detection thresholds are presented for ten benchmark circuits.