Design-for-testability for path delay faults in large combinatorial circuits using test-points

  • Authors:
  • Irith Pomeranz;Sudhakar M. Reddy

  • Affiliations:
  • Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA;Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA

  • Venue:
  • DAC '94 Proceedings of the 31st annual Design Automation Conference
  • Year:
  • 1994

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Abstract