AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
The interdependence between delay-optimization of synthesized networks and testing
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Compact test sets for digital logic circuits
Compact test sets for digital logic circuits
An efficient non-enumerative method to estimate path delay fault coverage
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Design-for-testability for path delay faults in large combinatorial circuits using test-points
DAC '94 Proceedings of the 31st annual Design Automation Conference
RESIST: a recursive test pattern generation algorithm for path delay faults
EURO-DAC '94 Proceedings of the conference on European design automation
Fast identification of robust dependent path delay faults
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On synthesis-for-testability of combinational logic circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Path delay ATPG for standard scan design
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits
IEEE Transactions on Computers
Test generation for path delay faults based on learning
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Oscillation Ring Delay Test for High Performance Microprocessors
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
INCREDYBLE: A New Search Strategy for Design Automation Problems with Applications to Testing
IEEE Transactions on Computers
Bit parallel test pattern generation for path delay faults
EDTC '95 Proceedings of the 1995 European conference on Design and Test
An efficient automatic test generation system for path delay faults in combinational circuits
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Test Generation for Path-Delay Faults in One-dimensional Iterative Logic Arrays
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Transition path delay faults: a new path delay fault model for small and large delay defects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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