Parallel pattern fault simulation of path delay faults
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
SPADES: a simulator for path delay faults in sequential circuits
EURO-DAC '92 Proceedings of the conference on European design automation
INCREDYBLE-TG: INCREmental DYnamic test generation based on LEarning
DAC '93 Proceedings of the 30th international Design Automation Conference
NEST: A non-enumerative test generation method for path delay faults in combinational circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Compact test sets for digital logic circuits
Compact test sets for digital logic circuits
Test generation for path delay faults based on learning
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
An efficient non-enumerative method to estimate path delay fault coverage
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
The Synthesis Approach to Digital System Design
The Synthesis Approach to Digital System Design
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Computational Aspects of VLSI
| Hi-index | 14.98 |
A new search strategy for design automation problems is proposed, that is directly applicable to circuits having a size parameter (e.g., operand size), and indirectly, to random-logic circuits as well. Under the proposed approach, exhaustive search for an optimal solution is performed for small versions of the target circuit, obtained by scaling-down all the size parameters of the circuit (e.g., by reducing the operand size). The optimal solutions obtained for the small circuits are studied, and analytic rules are derived to capture their common features. Using these rules, the solutions are scaled-up into a high-quality solution for the large target circuit. The method, its feasibility and limitations are described in this work. The method is applied to two problems related to testing of digital circuits, namely, test generation for stuck-at faults and test generation for path delay faults. Index Terms驴Combinational circuits, off-line testing, path delay faults, search strategy, stuck-at faults.