Parallel pattern fault simulation of path delay faults
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
The interdependence between delay-optimization of synthesized networks and testing
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
SPADES: a simulator for path delay faults in sequential circuits
EURO-DAC '92 Proceedings of the conference on European design automation
Graph Algorithms
NEST: A non-enumerative test generation method for path delay faults in combinational circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Design-for-testability for path delay faults in large combinatorial circuits using test-points
DAC '94 Proceedings of the 31st annual Design Automation Conference
An efficient path delay fault coverage estimator
DAC '94 Proceedings of the 31st annual Design Automation Conference
Path hashing to accelerate delay fault simulation
DAC '94 Proceedings of the 31st annual Design Automation Conference
RESIST: a recursive test pattern generation algorithm for path delay faults
EURO-DAC '94 Proceedings of the conference on European design automation
On synthesis-for-testability of combinational logic circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits
IEEE Transactions on Computers
SIGMA: a simulator for segment delay faults
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Test generation for path delay faults based on learning
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Reduction of Number of Paths to be Tested in Delay Testing
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
INCREDYBLE: A New Search Strategy for Design Automation Problems with Applications to Testing
IEEE Transactions on Computers
Resynthesis of Combinational Circuts for Path Count Reduction and for Path Delay Fault Testability
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Improving accuracy in path delay fault coverage estimation
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Parallel concurrent path-delay fault simulation using single-input change patterns
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Statistical path delay fault coverage estimation for synchronous sequential circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
20.1 A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A Flexible Path Selection Procedure for Path Delay Fault Testing
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Selection of Potentially Testable Path Delay Faults for Test Generation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
On Selecting Testable Paths in Scan Designs
Journal of Electronic Testing: Theory and Applications
Transition path delay faults: a new path delay fault model for small and large delay defects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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