Parallel pattern fault simulation of path delay faults
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Equivalence of robust delay-fault and single stuck-fault test generation
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
An efficient non-enumerative method to estimate path delay fault coverage
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Delay Testing for Non-Robust Untestable Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
An efficient architecture for accumulator-based test generation of SIC pairs
Microelectronics Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An effective two-pattern test generator for Arithmetic BIST
Computers and Electrical Engineering
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We present a new simulation-based method using single-input change (SIC) patterns to efficiently derive tests for singly-testable (ST) path-delay faults (PDFs). We assign random values to all inputs, and then propagate rising and falling transitions from each input while all other inputs are held steady. We present a sixteen-valued algebra with which rising and falling PDFs from all inputs are concurrently simulated. Using a suitable encoding for signal values, gates are evaluated directly through Boolean operations, and all computation stages use machine word parallelism. Results on, the ISCAS '85 and '89 benchmarks show that the method runs seven times faster than another published method (with normalized CPU times), and detects 76% more ST PDFs.