Delay fault coverage and performance tradeoffs
DAC '93 Proceedings of the 30th international Design Automation Conference
A Study of Theoretical Issues in the Synthesis of Delay Fault Testability Circuits
IEEE Transactions on Computers
A satisfiability-based test generator for path delay faults in combinational circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Test generation for primitive path delay faults in combinational circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Partial scan delay fault testing of asynchronous circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
On Redundant Path Delay Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
False-Path Removal Using Delay Fault Simulation
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Test Generation for Path Delay Faults Using Binary Decision Diagrams
IEEE Transactions on Computers
Parallel concurrent path-delay fault simulation using single-input change patterns
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Identifying Redundant Path Delay Faults in Sequential Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
9.2 On Delay-Untestable Paths and Stuck-Fault Redundancy
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
20.1 A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Delay Testing with Clock Control: An Alternative to Enhanced Scan
ITC '97 Proceedings of the 1997 IEEE International Test Conference
A new classification of path-delay fault testability in terms of stuck-at faults
Journal of Computer Science and Technology
Efficient path delay test generation based on stuck-at test generation using checker circuitry
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on τk-Notation
IEICE - Transactions on Information and Systems
Symbolic-Event-Propagation-Based Minimal Test Set Generation for Robust Path Delay Faults
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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