A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Provably correct critical paths
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
A Simulation-Based Method for Generating Tests for Sequential Circuits
IEEE Transactions on Computers
Equivalence of robust delay-fault and single stuck-fault test generation
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
An Efficient Implementation of Boolean Functions as Self-Timed Circuits
IEEE Transactions on Computers
Delay fault coverage and performance tradeoffs
DAC '93 Proceedings of the 30th international Design Automation Conference
Delay-insensitive multi-ring structures
Integration, the VLSI Journal - Special issue on asynchronous systems
Basic gate implementation of speed-independent circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Testing redundant asynchronous circuits by variable phase splitting
EURO-DAC '94 Proceedings of the conference on European design automation
Automatic generation of synchronous test patterns for asynchronous circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
Algorithms for Synthesis and Testing of Asynchronous Circuits
Algorithms for Synthesis and Testing of Asynchronous Circuits
Linear Test Times for Delay-Insensitive Circuits: a Compilation Strategy
Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Synchronous Test Generation Model for Asynchronous Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Synthesis for testability techniques for asynchronous circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect possible delay faults in a sequential asynchronous circuit. The delays that are to be tested must be provided by the synthesis system. By using this information a set of paths in the circuit that must be tested is identified (step 1). For these paths the circuit is made acyclic by inserting at least one scan latch in every cycle (step 2). Then test patterns are generated for these paths (step 3). These test patterns consist of setup and initialization vectors and the final test vector. We provide effective procedures to solve both the initialization and the test pattern generation problem. The latter problem is solved by reduction to a classical problem of stuck-at test pattern generation for a related combinational circuit. Finally, a heuristic is proposed to determine which state variables must become part of a scan chain, or for which input variables the positive and negative phase must be driven independently in test mode. Experimental results shows that a high level of path delay fault testability can be achieved with partial scan.