Provably correct critical paths
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Equivalence of robust delay-fault and single stuck-fault test generation
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Delay fault testing: trading fault coverage, test set size, and performance
Proceedings of the 1993 symposium on Research on integrated systems
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Design-for-testability for path delay faults in large combinatorial circuits using test-points
DAC '94 Proceedings of the 31st annual Design Automation Conference
RESIST: a recursive test pattern generation algorithm for path delay faults
EURO-DAC '94 Proceedings of the conference on European design automation
Synthesis of Delay-Verifiable Combinational Circuits
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Fast identification of robust dependent path delay faults
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On synthesis-for-testability of combinational logic circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits
IEEE Transactions on Computers
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Nyquist data converter testing and yield analysis using behavioral simulation
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Test generation for primitive path delay faults in combinational circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Partial scan delay fault testing of asynchronous circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
On primitive fault test generation in non-scan sequential circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
On Redundant Path Delay Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
Reduction of Number of Paths to be Tested in Delay Testing
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient Path Selection for Delay Testing Based on Path Clustering
Journal of Electronic Testing: Theory and Applications
Digital oscillation-test method for delay and stuck-at fault testing of digital circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Resynthesis of Combinational Circuts for Path Count Reduction and for Path Delay Fault Testability
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A Fast Optimal Robust Path Delay Fault Testable Adder
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Identifying Redundant Path Delay Faults in Sequential Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Primitive Path Delay Fault Identification
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
(Quasi-) Linear Path Delay Fault Tests for Adders
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
9.1 Efficient Path Selection for Delay Testing Based on Partial Path Evaluation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
9.3 Improving Path Delay Fault Testability by Path Removal
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
20.1 A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A Flexible Path Selection Procedure for Path Delay Fault Testing
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
TESTING OF CRITICAL PATHS FOR DELAY FAULTS
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Effective Path Selection for Delay Fault Testing of Sequential Circuits
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Delay Testing with Clock Control: An Alternative to Enhanced Scan
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Robust Testability of Primitive Faults using Test Points
ITC '99 Proceedings of the 1999 IEEE International Test Conference
What Does Robust Testing a Subset of Paths, Tell us about the Untested Paths in the Circuit?
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A Statistical Fault Coverage Metric for Realistic Path Delay Faults
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Diagnosis framework for locating failed segments of path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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