Parallel pattern fault simulation of path delay faults
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
The interdependence between delay-optimization of synthesized networks and testing
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Delay fault coverage and performance tradeoffs
DAC '93 Proceedings of the 30th international Design Automation Conference
Fast identification of robust dependent path delay faults
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Test Generation for Global Delay Faults
Proceedings of the IEEE International Test Conference on Test and Design Validity
Delay Testing for Non-Robust Untestable Circuits
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
9.1 Efficient Path Selection for Delay Testing Based on Partial Path Evaluation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
TESTING OF CRITICAL PATHS FOR DELAY FAULTS
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Speed Binning with Path Delay Test in 150-nm Technology
IEEE Design & Test
What Does Robust Testing a Subset of Paths, Tell us about the Untested Paths in the Circuit?
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
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In this paper, we introduce a way of modeling the differencesbetween the calculated delays and the real delays, and propose anefficient path selection method for path delay testing based on themodel. Path selection is done by judging which of two paths has thelarger real delay by taking into account the ambiguity of calculateddelay, caused by imprecise delay modeling as well as processdisturbances. In order to make precise judgment under this ambiguity,the delays of only the unshared segments of the two paths areevaluated. This is because the shared segments are presumed to havethe same real delays on both paths.The experiments used the delays of gates and interconnects, which werecalculated from the layout data of ISCAS85 benchmark circuits using areal cell library. Experimental results show the method selects only about one percent of the paths selected by the most popular method.