Accelerated transition fault simulation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Random Pattern Testability of Delay Faults
IEEE Transactions on Computers
Delay fault models and test generation for random logic sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Correlation-reduced scan-path design to improve delay fault coverage
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An efficient path delay fault coverage estimator
DAC '94 Proceedings of the 31st annual Design Automation Conference
Path hashing to accelerate delay fault simulation
DAC '94 Proceedings of the 31st annual Design Automation Conference
Fast identification of robust dependent path delay faults
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits
IEEE Transactions on Computers
Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits
Journal of Electronic Testing: Theory and Applications
An efficient non-enumerative method to estimate path delay fault coverage
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Efficient Path Selection for Delay Testing Based on Path Clustering
Journal of Electronic Testing: Theory and Applications
Robust and Nonrobust Path Delay Fault Simulation by Parallel Processing of Patterns
IEEE Transactions on Computers
INCREDYBLE: A New Search Strategy for Design Automation Problems with Applications to Testing
IEEE Transactions on Computers
An efficient method for computing exact path delay fault coverage
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Improving accuracy in path delay fault coverage estimation
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Parallel concurrent path-delay fault simulation using single-input change patterns
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
9.1 Efficient Path Selection for Delay Testing Based on Partial Path Evaluation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
9.3 Improving Path Delay Fault Testability by Path Removal
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Proceedings of the 17th ACM Great Lakes symposium on VLSI
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Fastpath: a path-delay test generator for standard scan designs
ITC'94 Proceedings of the 1994 international conference on Test
On path delay testing in a standard scan environment
ITC'94 Proceedings of the 1994 international conference on Test
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This paper presents an accelerated fault simulation approach for path delay faults. The distinct features of the proposed fault simulation method consist in the application of parallel processing of patterns at all stages of the calculation procedure, its versatility to account for both robust and non-robust detection of path delay faults, and its capability of efficiently maintaining large numbers of path faults to be simulated.