Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples

Authors:
Yun Shao;Sudhakar M. Reddy;Irith Pomeranz
Affiliations:
Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA;Electrical and Computer Engineering Department, University of Iowa, Iowa City, IA;School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
Venue:
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Year:
2002

Citing 10
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Abstract

In this work we propose a novel concept called state tuple to represent the states of lines in a circuit for the generation of two pattern tests.The proposed approach is described in detail for generating robust two pattern tests for path delay faults in standard scan designs.Using the proposed approach we also report experimental results of a test generator for robust path delay faults in standard scan designs.The results show that the test generator achieves high efficiency with reduced implementation complexity.