AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Synthesis and optimization procedures for robustly delay-fault testable combinational logic circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Introduction to Switching Theory and Logical Design
Introduction to Switching Theory and Logical Design
Robustly Scan-Testable CMOS Sequential Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
At-speed delay testing of synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Delay fault test generation for scan/hold circuits using Boolean expressions
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
RESIST: a recursive test pattern generation algorithm for path delay faults
EURO-DAC '94 Proceedings of the conference on European design automation
Path delay ATPG for standard scan design
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Test generation for delay faults in non-scan and partial scan sequential circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Delay fault testing of IP-based designs via symbolic path modeling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Generating Tests for Delay Faults in Nonscan Circuits
IEEE Design & Test
Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
Bit parallel test pattern generation for path delay faults
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
On Achieving Complete Coverage of Delay Faults in Full Scan Circuits using Locally Available Lines
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Delay Fault Testing of IP-Based Designs Via Symbolic Path Modeling
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Constraint extraction for pseudo-functional scan-based delay testing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Post-manufacture tuning for nano-CMOS yield recovery using reconfigurable logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fastpath: a path-delay test generator for standard scan designs
ITC'94 Proceedings of the 1994 international conference on Test
On path delay testing in a standard scan environment
ITC'94 Proceedings of the 1994 international conference on Test
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