DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Hierarchical timing analysis using conditional delays
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A satisfiability-based test generator for path delay faults in combinational circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Path delay fault testing of ICs with embedded intellectual property blocks
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Test Generation for Path Delay Faults Using Binary Decision Diagrams
IEEE Transactions on Computers
Fastpath: A Path-Delay Test Generator for Standard Scan Designs
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Scan chain design for test time reduction in core-based ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
High-coverage ATPG for datapath circuits with unimplemented blocks
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing Embedded Cores Using Partial Isolation Rings
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
1.1 Test methodology for embedded cores which protects intellectual property
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Delay Fault Testing of Designs with Embedded IP Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
NEST: a nonenumerative test generation method for path delay faults in combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
Predesigned blocks called intellectual property (IP) cores are increasingly used for complex system-on-a-chip (SOC) designs. The implementation details of IP cores are often unknown or unavailable, so delay testing of such designs is difficult. We propose a method that can test paths traversing both IP cores and user-defined blocks, an increasingly important but little-studied problem. It models representative paths in IP circuits using an efficient form of binary decision diagram (BDD) and generates test vectors from the BDD model. We also present a partitioning technique, which reduces the BDD size by orders of magnitude and makes the proposed method practical for large designs. Experimental results are presented which show that it robustly tests selected paths without using extra logic and, at the same time, protects the intellectual contents of IP cores.