Path delay fault testing of ICs with embedded intellectual property blocks

Testing systems on a chip

IEEE Spectrum

C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications

DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems

A Unifying Methodology for Intellectual Property and Custom Logic Testing

Proceedings of the IEEE International Test Conference on Test and Design Validity

Test Generation for Global Delay Faults

Proceedings of the IEEE International Test Conference on Test and Design Validity

An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded Cores

Proceedings of the IEEE International Test Conference

Test Requirements for Embedded Core-Based Systems and IEEE P1500

Proceedings of the IEEE International Test Conference

Testing Embedded Cores Using Partial Isolation Rings

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium

9.1 Efficient Path Selection for Delay Testing Based on Partial Path Evaluation

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

Delay fault coverage, test set size, and performance trade-offs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems