DAC '98 Proceedings of the 35th annual Design Automation Conference
Path delay fault testing of ICs with embedded intellectual property blocks
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Microprocessor based testing for core-based system on chip
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A new IEEE 1149.1 boundary scan design for the detection of delay defects
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Testing TAPed cores and wrapped cores with the same test access mechanism
Proceedings of the conference on Design, automation and test in Europe
Improving bus test via IDDT and boundary scan
Proceedings of the 38th annual Design Automation Conference
Built-in self-test for signal integrity
Proceedings of the 38th annual Design Automation Conference
On Concurrent Test of Core-Based SOC Design
Journal of Electronic Testing: Theory and Applications
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
Journal of Electronic Testing: Theory and Applications
Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores
Journal of Electronic Testing: Theory and Applications
Design and implementation of the "G2" PowerPC 603e-embedded microprocessor core
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A novel test methodology for core-based system LSIs and a testing time minimization problem
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Shared I/O-cell structures: a framework for extending the IEEE 1149.1 boundary-scan standard
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Genetic Algorithm based Test Scheduling and Test Access Mechanism Design for System-on-Chips
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
1.2 Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Instruction-Driven Wake-Up Mechanisms for Snoopy TAP Controller
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Considerations for Implementing IEEE 1149.1 on System-on-a-Chip Integrated Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Framework to evaluate Test Tradeoffs in Embedded Core Based Systems-Case Study on TT's TMS320C27xx
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An ILP Formulation to Optimize Test Access Mechanism in System-on-Chip Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Requirements for Embedded Core-based Systems and IEEE P1500
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Multi-TAP Controller Architecture for Digital System Chips
Journal of Electronic Testing: Theory and Applications
Trends in SLI design and their effect on test
ITC '99 Proceedings of the 1999 IEEE International Test Conference
HD-BIST: A Hierarchical Framework for BIST Scheduling and Diagnosis in SoCs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A Hierarchical Infrastructure for SoC Test Management
IEEE Design & Test
Searching for Global Test Costs Optimization in Core-Based Systems
Journal of Electronic Testing: Theory and Applications
Time Domain Multiplexed TAM: Implementation and Comparison
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Reusing an on-chip network for the test of core-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST
IEEE Transactions on Computers
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs
IEEE Transactions on Computers
Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip
Integration, the VLSI Journal
WSEAS Transactions on Circuits and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
An efficient link controller for test access to IP core-based embedded system chips
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
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