A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
An integrated system-on-chip test framework
Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Algorithms for VLSI Design Automation
Algorithms for VLSI Design Automation
Structural Fault Testing of Embedded Cores Using Pipelining
Journal of Electronic Testing: Theory and Applications
A Complete Strategy for Testing an On-Chip Multiprocessor Architecture
IEEE Design & Test
An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded Cores
Proceedings of the IEEE International Test Conference
Test Requirements for Embedded Core-Based Systems and IEEE P1500
Proceedings of the IEEE International Test Conference
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
Proceedings of the IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test wrapper and test access mechanism co-optimization for system-on-chip
Proceedings of the IEEE International Test Conference 2001
Solving capture in switched two-node Ethernets by changing only one node
LCN '95 Proceedings of the 20th Annual IEEE Conference on Local Computer Networks
A Study on Communication Issues for Systems-on-Chip
Proceedings of the 15th symposium on Integrated circuits and systems design
1.2 Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
The Impact of NoC Reuse on the Testing of Core-based Systems
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
On Using IEEE P1500 SECT for Test Plug-n-Play
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Set of Benchmarks fo Modular Testing of SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Effective and Efficient Test Architecture Design for SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Test Planning and Design Space Exploration in a Core-Based Environment
Proceedings of the conference on Design, automation and test in Europe
Efficient Wrapper/TAM Co-Optimization for Large SOCs
Proceedings of the conference on Design, automation and test in Europe
Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
SoCIN: A Parametric and Scalable Network-on-Chip
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Testing of core-based systems-on-a-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reuse-based test access and integrated test scheduling for network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A concurrent testing method for NoC switches
Proceedings of the conference on Design, automation and test in Europe: Proceedings
On reliable modular testing with vulnerable test access mechanisms
Proceedings of the 45th annual Design Automation Conference
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Re-examining the use of network-on-chip as test access mechanism
Proceedings of the conference on Design, automation and test in Europe
On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time
IEICE - Transactions on Information and Systems
NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints
IEICE - Transactions on Information and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Diagnosis of interconnect shorts in mesh NoCs
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism
Journal of Electronic Testing: Theory and Applications
Hardware-assisted dynamic power and thermal management in multi-core SoCs
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Early estimation of wire length for dedicated test access mechanisms in networks-on-chip based SoCs
Proceedings of the 24th symposium on Integrated circuits and systems design
Journal of Electronic Testing: Theory and Applications
A survey and taxonomy of on-chip monitoring of multicore systems-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test pin count reduction for NoC-based test delivery in multicore SOCs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Networks-on-chip are likely to become the main communication platform of systems-on-chip. To cope with the growing complexity of the test of such systems, the authors propose the reuse of the on-chip network as a test access mechanism to the cores embedded into systems that use this communication platform. An algorithm exploiting the network characteristics to minimize test time is presented. Then, the reuse strategy is evaluated considering a number of system configurations, such as different positions of the cores in the network, power consumption constraints and number of interfaces with the tester. Experimental results for the ITC'02 SOC Test Benchmarks show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized.