Introduction to algorithms
Reverse path forwarding of broadcast packets
Communications of the ACM
Structural Fault Testing of Embedded Cores Using Pipelining
Journal of Electronic Testing: Theory and Applications
Test Requirements for Embedded Core-Based Systems and IEEE P1500
Proceedings of the IEEE International Test Conference
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
Proceedings of the IEEE International Test Conference
Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
The Impact of NoC Reuse on the Testing of Core-based Systems
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Test Planning and Design Space Exploration in a Core-Based Environment
Proceedings of the conference on Design, automation and test in Europe
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Reusing an on-chip network for the test of core-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Bringing communication networks on a chip: test and verification implications
IEEE Communications Magazine
Indirect test architecture for SoC testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using the inter- and intra-switch regularity in NoC switch testing
Proceedings of the conference on Design, automation and test in Europe
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips
Proceedings of the 48th Design Automation Conference
Journal of Electronic Testing: Theory and Applications
Microprocessors & Microsystems
| Hi-index | 0.00 |
This paper proposes reuse of on-chip networks for testing switches in Network on Chips (NoCs). The proposed algorithm broadcasts test vectors of switches through the on-chip networks and detects faults by comparing output responses of switches with each other. This algorithm alleviates the need for: (1) external comparison of the output response of the circuit-under-test with the response of a fault free circuit stored on a tester (2) on-chip signature analysis (3) a dedicated test-bus to reach test vectors and collect their responses. Experimental results on a few test benches compare the proposed algorithm with traditional System on Chip (SoC) test methods.