Improving mixed-signal SOC testing: a power-aware reuse-based approach with analog BIST
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Searching for Global Test Costs Optimization in Core-Based Systems
Journal of Electronic Testing: Theory and Applications
Reusing an on-chip network for the test of core-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reuse-based test access and integrated test scheduling for network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A concurrent testing method for NoC switches
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Multiple-constraint driven system-on-chip test time optimization
Journal of Electronic Testing: Theory and Applications
Test exploration and validation using transaction level models
Proceedings of the Conference on Design, Automation and Test in Europe
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This paper proposes a comprehensive model for testplanning in a core-based environment. The main contributionof this work is the use of several types of TAMs and theconsideration of different optimization factors (area, pinsand test time) during the global TAM and test schedule definition.This expansion of concerns makes possible an efficientyet fine-grained search in the huge design space ofa reuse-based environment. Experimental results clearlyshow the variety of trade-offs that can be explored usingthe proposed model, and its effectiveness on optimizing thesystem test design.