Scheduling tests for VLSI systems under power constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
Test Scheduling and Test Access Architecture Optimization for System-on-Chip
ATS '02 Proceedings of the 11th Asian Test Symposium
On Test Scheduling for Core-Based SOCs
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
On Using IEEE P1500 SECT for Test Plug-n-Play
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Effective and Efficient Test Architecture Design for SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
On the Use of k-tuples for SoC Test Schedule Representation
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Test Planning and Design Space Exploration in a Core-Based Environment
Proceedings of the conference on Design, automation and test in Europe
Efficient Wrapper/TAM Co-Optimization for Large SOCs
Proceedings of the conference on Design, automation and test in Europe
On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Cluster-Based Test Architecture Design for System-on-Chip
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling
ETW '03 Proceedings of the 8th IEEE European Test Workshop
WSEAS Transactions on Circuits and Systems
Scheduling Power-Constrained Tests through the SoC Functional Bus
IEICE - Transactions on Information and Systems
Test Scheduling for Core-Based SOCs Using Genetic Algorithm Based Heuristic Approach
ICIC '07 Proceedings of the 3rd International Conference on Intelligent Computing: Advanced Intelligent Computing Theories and Applications. With Aspects of Artificial Intelligence
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The cost of testing SOCs (systems-on-chip) is highly related to the test application time. The problem is that the test application time increases as the technology makes it possible to design highly complex chips. These complex chips include a high number of fault sites, which need a high test data volume for testing, and the high test data volume leads to long test application times. For modular core-based SOCs where each module has its distinct tests, concurrent application of the tests can reduce the test application time dramatically, as compared to sequential application. However, when concurrent testing is used, resource conflicts and constraints must be considered. In this paper, we propose a test scheduling technique with the objective to minimize the test application time while considering multiple conflicts. The conflicts we are considering are due to cross-core testing (testing of interconnections between cores), module testing with multiple test sets, hierarchical conflicts in SOCs where cores are embedded in cores, the sharing of the TAM (test access mechanism), test power limitations, and precedence conflicts where the order in which tests are applied is important. These conflicts must be considered in order to design a test schedule that can be used in practice. In particular, the limitation on the test power consumption is important to consider since exceeding the system's power limit might damage the system. We have implemented a technique to integrate the wrapper design algorithm with the test scheduling algorithm, while taking into account all the above constraints. Extensive experiments on the ITC' 02 benchmarks show that even though we consider a high number of constraints, our technique produces results that are in the range of results produced be techniques where the constraints are not taken into account.