Multiple-constraint driven system-on-chip test time optimization
Journal of Electronic Testing: Theory and Applications
Test infrastructure design for mixed-signal SOCs with wrapped analog cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
STEAC: a platform for automatic SOC test integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SOC test architecture and method for 3-D ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
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We propose an efficient test scheduling and test access architecturefor system-on-chip. The test time and test controlcomplexity are optimized under the test power and TAM resourceconstraints. Using our heuristic algorithms, the testscheduling can be done rapidly with small test time penaltywhen compared with previous works. Under an existing SOCtest framework, the test access hardware can be generatedfrom the scheduling result. Experimental results show thatthe proposed scheduling is hardware efficient. The systemintegrator can evaluate the test access architecture and performtest scheduling systematically.