SOC test architecture and method for 3-D ICs

Authors:
Chih-Yen Lo;Yu-Tsao Hsing;Li-Ming Denq;Cheng-Wen Wu
Affiliations:
Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan;Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan;Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan;Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Year:
2010

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Abstract

3-D integration provides another way to put more devices in a smaller footprint. However, it also introduces new challenges in testing. Flexible test architecture named test access control system for 3-D integrated circuits (TACS-3D) is proposed for 3-D integrated circuits (IC) testing. Integration of heterogeneous design-for-testability methods for logic, memory, and through-silicon via (TSV) testing further reduces the usage of test pins and TSVs. To highly reuse pre-bond test circuits in post-bond test, an innovative linking mechanism shares TSVs and test pins of the 3-D IC. No matter how many layers are there in the 3-D IC, a large portion of TSVs and test pins is reserved for data application. Therefore, smaller post-bond test time is expected. A test chip composed of a network security processor platform is taken as an example. Less than 0.4% test overhead increases in area and time between 2-D and 3-D cases. Compared with the instinctively direct access, TACS-3D reveals up to 54% test time improvement under the same TSV usage.