Test Challenges for 3D Integrated Circuits

Authors:
Hsien-Hsin S. Lee;Krishnendu Chakrabarty
Affiliations:
Georgia Institute of Technology;Duke University
Venue:
IEEE Design & Test
Year:
2009

Citing 0
Cited 21

Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint

Proceedings of the 2009 International Conference on Computer-Aided Design
Test-access mechanism optimization for core-based three-dimensional SOCs

Microelectronics Journal
TSV redundancy: architecture and design issues in 3D IC

Proceedings of the Conference on Design, Automation and Test in Europe
SOC test architecture and method for 3-D ICs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Assembling 2D blocks into 3D chips

Proceedings of the 2011 international symposium on Physical design
Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis

Proceedings of the International Conference on Computer-Aided Design
Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system

Proceedings of the International Conference on Computer-Aided Design
Optimization Methods for Post-Bond Testing of 3D Stacked ICs

Journal of Electronic Testing: Theory and Applications
Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost

Journal of Electronic Testing: Theory and Applications
Scheduling Tests for 3D Stacked Chips under Power Constraints

Journal of Electronic Testing: Theory and Applications
A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

Journal of Electronic Testing: Theory and Applications
Three-dimensional Integrated Circuits: Design, EDA, and Architecture

Foundations and Trends in Electronic Design Automation
TSV open defects in 3D integrated circuits: characterization, test, and optimal spare allocation

Proceedings of the 49th Annual Design Automation Conference
Post-bond stack testing for 3d stacked IC

VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis

Journal of Electronic Testing: Theory and Applications
Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels

Proceedings of the Conference on Design, Automation and Test in Europe
TSV redundancy: architecture and design issues in 3-D IC

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Integrated test-architecture optimization and thermal-aware test scheduling for 3-D SoCs under pre-bond test-pin-count constraint

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On effective TSV repair for 3D-stacked ICs

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A thermal-driven test application scheme for pre-bond and post-bond scan testing of three-dimensional ICs

ACM Journal on Emerging Technologies in Computing Systems (JETC)
A Novel Wafer Manipulation Method for Yield Improvement and Cost Reduction of 3D Wafer-on-Wafer Stacked ICs

Journal of Electronic Testing: Theory and Applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

Editor's note:One of the challenges for 3D technology adoption is the insufficient understanding of 3D testing issues and the lack of DFT solutions. This article describes testing challenges for 3D ICs, including problems that are unique to 3D integration, and summarizes early research results in this area.—Yuan Xie, Pennsylvania State University