Multilevel hypergraph partitioning: applications in VLSI domain
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel scan architecture for power-efficient, rapid test
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Thermal-Aware Test Scheduling and Hot Spot Temperature Minimization for Core-Based Systems
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Thermal analysis of a 3D die-stacked high-performance microprocessor
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Design space exploration for 3D architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction
IEEE Transactions on Computers
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
Journal of Electronic Testing: Theory and Applications
Scan-chain design and optimization for three-dimensional integrated circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
The ATPG Conflict-Driven Scheme for High Transition Fault Coverage and Low Test Cost
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Opportunities and Challenges for 3D Systems and Their Design
IEEE Design & Test
Test Challenges for 3D Integrated Circuits
IEEE Design & Test
Scan-chain partition for high test-data compressibility and low shift power under routing constraint
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification
ATS '09 Proceedings of the 2009 Asian Test Symposium
Thermal-Aware Task Scheduling for 3D Multicore Processors
IEEE Transactions on Parallel and Distributed Systems
Proceedings of the 2009 International Conference on Computer-Aided Design
QC-fill: quick-and-cool X-filling for multicasting-based scan test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures
Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures
A novel test application scheme for high transition fault coverage and low test cost
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Test architecture design and optimization for three-dimensional SoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Selective Test Response Collection for Low-Power Scan Testing with Well-Compressed Test Data
ATS '11 Proceedings of the 2011 Asian Test Symposium
MVP: capture-power reduction with minimum-violations partitioning for delay testing
Proceedings of the International Conference on Computer-Aided Design
Placement of thermal vias in 3-D ICs using various thermal objectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ISAC: Integrated Space-and-Time-Adaptive Chip-Package Thermal Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Efficient Scan Tree Design for Compact Test Pattern Set
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scan Architecture With Align-Encode
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cost-Effective Power-Aware Core Testing in NoCs Based on a New Unicast-Based Multicast Scheme
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The three-dimensional (3-D) technology offers a new solution to the increasing density of integrated circuits (ICs). In this work, we propose novel scan architectures for 3-D IC pre-bond and post-bond testing by considering the interconnection overhead of through-silicon-vias (TSVs). Since hotspots in 3-D ICs often cause performance and reliability issues, we also develop different test ordering schemes for prebond and postbond testing to avoid applying test vectors that could worsen the temperature distribution. Experimental results show that the peak temperature can be lowered by 20% with the 3-D scan tree architecture. When combined with the test ordering scheme, the 3-D scan tree can further reduce peak temperature by over 30%.