Three-dimensional multiprocessor system-on-chip thermal optimization
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Reliable multiprocessor system-on-chip synthesis
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Temperature-aware voltage selection for energy optimization
Proceedings of the conference on Design, automation and test in Europe
Application-specific MPSoC reliability optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Temperature-aware test scheduling for multiprocessor systems-on-chip
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
ThermalScope: multi-scale thermal analysis for nanometer-scale integrated circuits
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Stochastic thermal simulation considering spatial correlated within-die process variations
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Online work maximization under a peak temperature constraint
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Proceedings of the 46th Annual Design Automation Conference
Multiscale thermal analysis for nanometer-scale integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Architecture-level thermal characterization for multicore microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Temperature-aware idle time distribution for energy optimization with dynamic voltage scaling
Proceedings of the Conference on Design, Automation and Test in Europe
Multi-temperature testing for core-based system-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Properties of and improvements to time-domain dynamic thermal analysis algorithms
Proceedings of the Conference on Design, Automation and Test in Europe
TABS: temperature-aware layout-driven behavioral synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Run-time adaptable on-chip thermal triggers
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Full-chip thermal analysis for the early design stage via generalized integral transforms
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-energy automated scheduling of computing resources
Proceedings of the 1st ACM/IEEE workshop on Autonomic computing in economics
Proceedings of the 48th Design Automation Conference
Temperature aware statistical static timing analysis
Proceedings of the International Conference on Computer-Aided Design
Full-chip runtime error-tolerant thermal estimation and prediction for practical thermal management
Proceedings of the International Conference on Computer-Aided Design
Three-dimensional Integrated Circuits: Design, EDA, and Architecture
Foundations and Trends in Electronic Design Automation
Thermal Characterization of Test Techniques for FinFET and 3D Integrated Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints
Journal of Electronic Testing: Theory and Applications
NUMANA: a hybrid numerical and analytical thermal simulator for 3-D ICs
Proceedings of the Conference on Design, Automation and Test in Europe
Temperature-aware idle time distribution for leakage energy optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient method for analyzing on-chip thermal reliability considering process variations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design space exploration of FinFET cache
ACM Journal on Emerging Technologies in Computing Systems (JETC)
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Process-Variation and Temperature Aware SoC Test Scheduling Technique
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.03 |
Ever-increasing integrated circuit (IC) power densities and peak temperatures threaten reliability, performance, and economical cooling. To address these challenges, thermal analysis must be embedded within IC synthesis. However, this requires accurate three-dimensional chip-package heat flow analysis. This has typically been based on numerical methods that are too computationally intensive for numerous repeated applications during synthesis or design. Thermal analysis techniques must be both accurate and fast for use in IC synthesis. This paper presents a novel accurate incremental spatially and temporally adaptive chip-package thermal analysis technique called ISAC for use in IC synthesis and design. It is common for IC temperature variation to strongly depend on position and time. ISAC dynamically adapts spatial- and temporal-modeling granularities to achieve high efficiency while maintaining accuracy. Both steady-state and dynamic thermal analyses are accelerated by the proposed heterogeneous spatial-resolution adaptation and asynchronous thermal-element time-marching techniques. Each technique enables orders-of-magnitude improvement in performance while preserving accuracy when compared with other state-of-the-art adaptive steady-state and dynamic IC thermal analysis techniques. Experimental results indicate that these improvements are sufficient to make accurate dynamic and steady-state thermal analysis practical within the inner loops of IC synthesis algorithms. ISAC has been validated against reliable commercial thermal analysis tools using industrial and academic synthesis test cases and chip designs. It has been implemented as a software package suitable for integration in IC synthesis and design flows and has been publicly released