Confidence estimation for speculation control
Proceedings of the 25th annual international symposium on Computer architecture
Model order-reduction of RC(L) interconnect including variational analysis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Low power sequential circuit design by using priority encoding and clock gating
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
3D thermal-ADI: an efficient chip-level transient thermal simulator
Proceedings of the 2003 international symposium on Physical design
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Predictive dynamic thermal management for multimedia applications
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Dynamic Thermal Management for High-Performance Microprocessors
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Temperature-aware microarchitecture: Modeling and implementation
ACM Transactions on Architecture and Code Optimization (TACO)
Performance, Energy, and Thermal Considerations for SMT and CMP Architectures
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Analytical Model for Sensor Placement on Microprocessors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Techniques for Multicore Thermal Management: Classification and New Exploration
Proceedings of the 33rd annual international symposium on Computer Architecture
Systematic temperature sensor allocation and placement for microprocessors
Proceedings of the 43rd annual Design Automation Conference
HybDTM: a coordinated hardware-software approach for dynamic thermal management
Proceedings of the 43rd annual Design Automation Conference
Balancing power consumption in multiprocessor systems
Proceedings of the 1st ACM SIGOPS/EuroSys European Conference on Computer Systems 2006
Temperature-aware processor frequency assignment for MPSoCs using convex optimization
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Proactive temperature balancing for low cost thermal management in MPSoCs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Static and dynamic temperature-aware scheduling for multiprocessor SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proactive Speed Scheduling for Real-Time Tasks under Thermal Constraints
RTAS '09 Proceedings of the 2009 15th IEEE Symposium on Real-Time and Embedded Technology and Applications
Energy-efficient variable-flow liquid cooling in 3D stacked architectures
Proceedings of the Conference on Design, Automation and Test in Europe
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISAC: Integrated Space-and-Time-Adaptive Chip-Package Thermal Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing Thermal Sensor Allocation for Microprocessors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Unified reliability estimation and management of NoC based chip multiprocessors
Microprocessors & Microsystems
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With ever-increasing power densities, Dynamic Thermal Management (DTM) techniques have become mainstream in today's systems. An important component of such techniques is the thermal trigger. It has been shown that predictive thermal triggers can outperform reactive ones [4]. In this paper, we present a novel trade-off space of predictive thermal triggers, and compare different approaches proposed in the literature. We argue that run-time adaptability is a crucial parameter of interest. We present a run-time adaptable thermal simulator compatible with arbitrary sensor configuration based on the Neural Network (NN) simulator presented in [14]. We present experimental results on Niagara UltraSPARC T1 chip with real-life benchmark applications. Our results quantitatively establish the effectiveness of the proposed simulator for reducing (by up to 90%), the otherwise unacceptably high errors, that can arise due to expected leakage current variation and design-time thermal modeling errors.