Model order-reduction of RC(L) interconnect including variational analysis

Impact of interconnect variations on the clock skew of a gigahertz microprocessor

Proceedings of the 37th Annual Design Automation Conference

Explicit computation of performance as a function of process variation

Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems

Model reduction of variable-geometry interconnects using variational spectrally-weighted balanced truncation

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design

An efficient DC-gain matched balanced truncation realization for VLSI Interconnect circuit order reduction

Microelectronic Engineering

Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations

ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design

A linear fractional transform (LFT) based model for interconnect parametric uncertainty

Proceedings of the 41st annual Design Automation Conference

Variational delay metrics for interconnect timing analysis

Proceedings of the 41st annual Design Automation Conference

Parametric reduced order modeling for interconnect analysis

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

Fast interval-valued statistical interconnect modeling and reduction

Proceedings of the 2005 international symposium on Physical design

A quasi-convex optimization approach to parameterized model order reduction

Proceedings of the 42nd annual Design Automation Conference

Interval-valued reduced order statistical interconnect modeling

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Variational interconnect analysis via PMTBR

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Stochastic analysis of interconnect performance in the presence of process variations

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Statistical crosstalk aggressor alignment aware interconnect delay calculation

Proceedings of the 2006 international workshop on System-level interconnect prediction

Parameterized block-based non-gaussian statistical gate timing analysis

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Variational Interconnect Delay Metrics for Statistical Timing Analysis

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design

Statistical gate delay calculation with crosstalk alignment consideration

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI

Parameterized model order reduction of nonlinear dynamical systems

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

A practical method to estimate interconnect responses to variabilities

Proceedings of the conference on Design, automation and test in Europe: Proceedings

Design and verification of high-speed VLSI physical design

Journal of Computer Science and Technology

Performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Random sampling of moment graph: a stochastic Krylov-reduction algorithm

Proceedings of the conference on Design, automation and test in Europe

Statistical model order reduction for interconnect circuits considering spatial correlations

Proceedings of the conference on Design, automation and test in Europe

A frequency-domain technique for statistical timing analysis of clock meshes

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Parameterized model order reduction via a two-directional Arnoldi process

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Deep submicron interconnect timing model with quadratic random variable analysis

Proceedings of the conference on Design, automation and test in Europe

Generating reduced order models using subspace iteration for linear RLC circuits in nanometer designs

Proceedings of the 2nd international conference on Nano-Networks

Statistical analysis of on-chip power grid networks by variational extended truncated balanced realization method

Proceedings of the 2009 Asia and South Pacific Design Automation Conference

Fast variational interconnect delay and slew computation using quadratic models

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Evenly distributed RC interconnect ELO model simplification and its simulation

International Journal of Modelling and Simulation

Statistical analysis of large on-chip power grid networks by variational reduction scheme

Integration, the VLSI Journal

SPARE: a scalable algorithm for passive, structure preserving, parameter-aware model order reduction

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip

Run-time adaptable on-chip thermal triggers

Proceedings of the 16th Asia and South Pacific Design Automation Conference

Performance-oriented parameter dimension reduction of VLSI circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Model order reduction of fully parameterized systems by recursive least square optimization

Proceedings of the International Conference on Computer-Aided Design