Efficient reduced-order modeling for the transient simulation of three-dimensional interconnect
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Model-reduction of nonlinear circuits using Krylov-space techniques
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model order-reduction of RC(L) interconnect including variational analysis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Geometrically parameterized interconnect performance models for interconnect synthesis
Proceedings of the 2002 international symposium on Physical design
Analysis of Multiconductor Transmission Lines
Analysis of Multiconductor Transmission Lines
Parametric reduced order modeling for interconnect analysis
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Full-wave analysis of high-speed interconnects using complex frequency hopping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simulation of high-speed distributed interconnects using Krylov-space techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
This paper presents a model order reduction technique using subspace iterative scheme for high speed coupled integrated circuit interconnects in nanometer designs. The salient feature of this technique is less complexity in computation of a few smallest poles of the reduced order model. This paper shows that the subspace iterative scheme produces reduced systems that accurately follow the time- and frequency- domain responses of the original system. Experimental results show that the subspace iterative scheme achieves more accuracy than the variational Krylov-subspace-based model order reduction techniques. Significant reduction in computational expense is achieved as the size of the reduced equations is much less than that of the original system.